Cypress Semiconductor /psoc63 /I2S0 /RX_FIFO_CTL

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Interpret as RX_FIFO_CTL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TRIGGER_LEVEL0 (CLEAR)CLEAR 0 (FREEZE)FREEZE

Description

RX FIFO control

Fields

TRIGGER_LEVEL

Trigger level. When the RX FIFO has more entries than the number of this field, a receiver trigger event is generated. Note: software can configure up to 253 in I2S mode or Left Justified (RX_CTL.I2S_MODE = ‘0’ or ‘1’). In TDM mode (RX_CTL.I2S_MODE = ‘2’ or ‘3’), it can configure up to [256 - (RX_CTL.CH_NR+2)].

CLEAR

When ‘1’, the RX FIFO and RX_BUF are cleared/invalidated. Invalidation will last for as long as this field is ‘1’. If a quick clear/invalidation is required, the field should be set to ‘1’ and be followed by a set to ‘0’. If a clear/invalidation is required for an extended time period, the field should be set to ‘1’ during the complete time period.

FREEZE

When ‘1’, hardware writes to the RX FIFO have no effect. Freeze will not advance the RX FIFO write pointer. This field is used only for debugging purposee.

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